Business Wire

Mentor Graphics Questa Vanguard Program Drives Expansion of SystemVerilog Ecosystem; Third-Party Verification IP Qualified with Questa

Sutherland HDL, Inc. "Sutherland HDL, a leader in advanced SystemVerilog training, has been pleased to use Questa in our training workshops, and to be an evaluator of Questa 6.2 and AVM. Questa ...
EDN

Using advanced logging techniques to debug & test SystemVerilog HDL code

SystemVerilog provides an advantage in addressing the verification complexity challenge—not simply as a new language for describing complex structures, but as a platform for driving a more efficient, ...
EDN

Delivering advanced SystemVerilog verification capabilities to design teams

Some might say you need to be a full-fledged verification expert or specialist with experience using the latest object-oriented languages to tap into the productivity benefits of advanced verification ...
Design-Reuse

TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite

Eastleigh UK - Paris France, January 24, 2005 – TransEDA, the leader in coverage and ready-to-use verification solutions for electronic designs, today announces SystemVerilog support in new versions ...
Design-Reuse

Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization

MOUNTAIN VIEW, Calif., July 26, 2006--Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that it has donated a library of advanced SystemVerilog assertion ...
GlobalSpec

Appendix B: Verilog and SystemVerilog Reserved Keywords

The SystemVerilog-2005 standard is an extension to the Verilog-2005 standard. As part of this extension, SystemVerilog adds several new keywords to Verilog. This appendix lists: The original ...
GlobalSpec

Appendix C: A History of SUPERLOG, the Beginning of SystemVerilog

Reflecting the syntax and semantic changes to the SystemVerilog language, this text explains the SystemVerilog "packages," summarizes the synthesis guidelines presented throughout, and contains code ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...
ADVFN

Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization

"As the SystemVerilog leader, Synopsys has provided its customers with advanced assertion checkers for several years to enable higher designer productivity and faster adoption of assertion-based ...